About - Screenshots - Documentation - Requirements - Download - Resources - Contact
04. Mai 2004 The signs project has been proted to java and moved to a new home! New Signs Home
11. Okt. 2002 Initial import to CVS. You can checkout signs sources now.
10. Okt. 2002 Launch of signs's home at sourceforge.net
Aug. 2002 Light! First lines of signs were coded.
About
"Signs" stands for "Simple Gate Net Simulator".
The project goal is to provide a set of tools for gate-level logic synthesis, analysis and simulation, based on a subset of VHDL. This includes gnc, the gate net compiler which understands an easily synthesizable subset of VHDL (but includes behavioural VHDL constructs) and gns, the gate net simulator and analyzer which provides a graphical netlist viewer and an event-based gatelevel simulator. More tools may be added later, especially place+route tools to generate FPGA programming data are planned.
Signs is, at least for now, mainly aimed at teaching/educational purposes and not yet suited for production circuit design. Most developement will is done the C programming language, glib and gtk+ are used as a portability layer and gui environment. Unix/Linux-like platforms are the main target of developement, but the plan is to keep signs portable to other platforms as well.
Contributions highly appreciated. Feel free to contact us.
Screenshots
 Detailed view of a design, one signal selected. |
 Simulating a carry lookahead adder, adding one to one |
glib and gtk 1.2
Download
Latest Release: none yet
To get a cvs snapshot, try:
cvs -d :pserver:anonymous@cvs.signs.sourceforge.net:/cvsroot/signs login cvs -d :pserver:anonymous@cvs.signs.sourceforge.net:/cvsroot/signs co signs
©2002 by the signs project - last change: 11.10.2002